1. Technical Field
The present invention relates to a semiconductor device and, more particularly, to an output driver for use in a semiconductor device capable of outputting internal data of the semiconductor device to the exterior of a chip.
2. Discussion of the Related Art
Semiconductor devices, such as microcomputers, memory devices, gate arrays and the like, are used in a variety of electrical products such as personal computers, workstations and the like. Such semiconductor devices have input/output pins for transmitting and receiving data to and from external circuits, and an output circuit for providing internal data to external circuits, for example, an output buffer and an output driver circuit. When the semiconductor devices are incorporated in the electrical products, the input/output pins are connected to a transmission line such as a printed wiring on a mounted substrate, and the internal data of the semiconductor device is provided to other semiconductor devices through the transmission line as an interface. In this case, in order that output data of the semiconductor device is optimally transmitted via the transmission line, matching between an output impedance of the input/output pins and an impedance of the transmission line should be performed.
In particular, for a semiconductor device requiring a high-speed operation such as an SRAM (Static Random Access Memory), small swing to reduce a swing width of a signal is employed in order to minimize a delay time required for signal delivery and to reduce consumption power. However, as the swing width of the signal is reduced, an effect due to an external noise increases and reflection of an output signal due to impedance mismatching in an interface stage becomes critical. The impedance mismatching is caused by an external noise or a change of power supply voltage, a change of operating temperature, a change of manufacturing process, or the like. Occurrence of impedance mismatching makes high-speed data transmission difficult and may distort a signal outputted from a data output terminal of, the semiconductor device, namely, output data. Accordingly, if a semiconductor device at a receiving side receives the distorted output signal at its input, it causes problems, such as setup/hold fail, determination miss for an input level, or the like.
Hereinafter, configurations and operations of an impedance control circuit and an output circuit for use in a semiconductor memory device will be discussed, in connection with an output driver for use in a semiconductor device in accordance with prior art.
FIG. 1 is a block diagram showing an impedance control circuit (ZQ circuit) and an output circuit for use in a semiconductor device, and FIG. 2 is a circuit diagram showing an output driver for use in a semiconductor device in accordance with prior art. The configuration and operation of the impedance control circuit for use in the semiconductor device will be briefly described with reference to FIGS. 1 and 2.
The impedance control circuit in FIG. 1 is composed of an impedance detector 110, an impedance comparator 120, a counter 130, a high-level code selector (HCS) 140, and a ZQ driver 150. The output circuit is composed of a data output buffer 160 and an off-chip driver 170 that is an output driver. An external resistor RZQ having a resistance value of about five times the impedance value of an external device is connected between an extra pad ZQPAD of the impedance detector 110 and ground, and the impedance ZQ detector 110 outputs a pad voltage ZQPAD and a reference voltage REFIO. Generally, a level of the reference voltage REFIO is preset to a level of half the output power supply voltage VDDQ/2. The impedance comparator 120 compares the level of the reference voltage REFIO with the level of the pad voltage ZQPAD, and outputs a resultant up-down control signal UDZQ. The counter 130 performs up or down counting in response to the up-down control signal UDZQ, and outputs a control code data CTQx for selectively, placing a MOS array composed of a plurality of MOS transistors at a turn-on or off state. Also, the counter 130 performs a counting operation that increases or decreases the control code data CTQx until the level of the reference voltage REFIO and the level of the pad voltage ZQPAD become the same. Accordingly, the selected MOS transistors are turned on or off, such that the level of the reference voltage REFIO and the level of the pad voltage ZQPAD become identical. In this case, the reference voltage REFIO and the pad voltage ZQPAD become at the same level of VDDQ/2, and a turn-on resistance value of the MOS array and a resistance value of the external resistance RZQ become identical with each other. Consequently, transistors in the off-chip driver 170 are turned on as MOS transistors in the MOS array that are determined to be turned on, resulting in the match of the output impedance with an external impedance. The high-level code selector 140 outputs high-level control code data CTQDx by selecting high-level control code data from a plurality of control code data CTQx that are received in the impedance matching process. The ZQ driver 150 generates driving code data CZQx in response to the selected control code data CTQDx and provides the data to the data output buffer 160 when the off-chip driver 170 is in a high impedance state. Accordingly, previous driving code data CZQx is newly updated according to a change of the selected control code data CTQDx. The updated driving code data CZQx is applied to the data output buffer 160, and only a unit buffer selected from unit buffers in the data output buffer 160 is enabled in response to the updated driving code data CZQx. Accordingly, the enabled unit buffer in the data output buffer 160 receives DATA/DATAB being internal data to be outputted to the exterior, generates pull-up output data DOUx and pull-down output data DODx, and applies them to the off-chip driver 170. Accordingly, a signal level of final output data is determined by the selected transistors in the off-chip driver 170 and is provided to the exterior via the output terminal DQ. An output impedance value for the output data becomes identical with an impedance of an external device through the above-stated impedance control process, thus achieving the impedance matching.
As shown in FIG. 2, the off-chip driver 170 is composed of a pull-up driving section including a first PMOS and a first NMOS transistors 172 and 174 for determining a state of a first node N1 in response to pull-up output data DOUx and a pull-up driving transistor 180 operating according to the state of the first node N1; and a pull-down driving section including a second PMOS and a second NMOS transistors 176 and 178 for determining a state of a second node N2 in response to a pull-down output data DODx and a pull-down driving transistor 182 operating according to the state of the second node N2. The pull-up driving transistor 180 is connected between a third node N3 and an external power supply VDDQ, and is turned on when the first node N1 is in a “L” state, serving to provide an output terminal with the output data. Further, the pull-down driving transistor 182 is connected between a third node N3 and a ground power supply VSSQ, and is turned on when the second node N2 is in a “H” state, serving to provide the output terminal with the output data.
The external power supply VDDQ of the output driver in accordance with the above-described prior art is provided in a voltage level lower than that used by other circuits in a chip in order to embody a small swing interface. In this case, a problem arises in that the external power supply voltage VDDQ provided to an output driver changes with a change of the external voltage, and in turn, an impedance for the output data changes correspondingly. Therefore, since the output data is distorted and outputted, problems arise, such as a setup/hold fail, determination miss for an input level, and the like when the external device receives the distorted output signal.